What You'll Do:

The Systems Architecture Lab is exploring technologies to address the memory and communication walls in HPC and AI systems.

Data driven computation has grown explosively over the past decade, as evidenced by the emergence of many big data science, analytics and machine learning frameworks and platforms optimized for those frameworks. Three of the most prominent analytics and machine learning methods employed in state of the art data science frameworks are: Graph analytic, Graph Neural Network, and Transformer Networks. The common data attribute shared by these three use cases is massive sparse compressed data, irregular fine grain access patterns, dynamically evolving data structures, and in many cases little data reuse opportunity. The common computational abstraction at the heart of these methods is sparse tensor algebra. Commercially relevant graph analytics and graph neural network use cases can be 100's of TB's or even PB's of data. In many cases the data set is also in motion at high velocity, such as electronic payment systems, social media platforms, automated manufacturing floors and, power grids.

Given these trends, it is not surprising that interest in general accelerators for sparse tensor algebra is increasing. Sparse tensor algebra, expressed with tensor index notation, is an important language with a long history, starting as a mathematical notation. It has recently gained traction as a computational language that subsumes linear algebra. Recent academic research has defined an abstract machine model called the Sparse Abstract Machine. SAM consists of dataflow blocks that lend themselves to VLSI, FPGA, or CGRA implementation. SAM is to dataflow accelerators as an ISA is to a conventional processor. It provides an interface between the hardware and compiler, allowing the end-to-end system to continue to function while both sides are optimized

In this project the summer intern will map SAM onto a possible CGRA, optimize and validate its performance on sparse tensor algebra code.

Location: Hybrid, working onsite at our San Jose headquarters 3 days per week, with the flexibility to work remotely the remainder of your time or Fully Remote, with the opportunity to work from home
Reports to: Vice President, Chief Hardware Architect of HPC

• Map SAM onto a CGRA architecture
• Optimize and validate its performance on sparse tensor algebra code
• Identify potential optimization to the code generator

What You Bring

• PhD student in Computer Science or Engineering
• Domain expertise in Sparse Tensor Algebra and optimized implementations on novel hardware platforms
• Familiarity with dataflow and/or CGRA accelerators preferred
• Familiarity with DSL Compiler technology, TACO in particular preferred
• You're inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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